Field of the Invention
The present invention generally relates to a communication protocol between a memory controller and memory and, more specifically, to a time-multiplexed communication protocol for transmitting a command and address between a memory controller and a multi-port memory device.
Description of the Related Art
The burst length of a memory transaction between a memory controller and a memory such as a dynamic random access memory (DRAM) is determined by the ratio between a first and second frequency. The first frequency is the frequency of the memory interface between a conventional processor and the DRAM. The second frequency is the frequency at which the DRAM core operates. While the second frequency has remained relatively constant, the first frequency has increased with each new generation of DRAM. For example, double data rate (DDR) DRAM that performs four data transfers per clock cycle, e.g., DDR2, uses a minimum burst length of 4 and DDR3 uses a minimum burst length of 8. Assuming the trend continues, the next generation of DRAM may have a minimum burst length of 16 or higher.
As the minimum burst length increases, the minimum amount of data that is transmitted over the memory interface between the DRAM and the processor during a burst, also referred to as “the minimum burst size,” increases. For example, the minimum burst size for a 32-bit data interface having a minimum burst length of 8 is 32 bytes. When the minimum burst length increases from 8 to 16, the minimum burst size increases to 64 bytes. Some conventional processors are architected to access data in 32 byte increments. Additionally, the 32 byte increments may not be stored in adjacent memory locations within the DRAM. When the amount of data that is transmitted over the memory interface between the DRAM and the processor during a burst increases from 32 bytes to 64 bytes half of the data may not be needed and is discarded by the processor.
One approach to dealing with the above problem would be to re-architect conventional processors to access data in 64 byte or larger increments. In most scenarios due to underlying constraints, re-architecting is only able to recover part of loss in utilization. Also, as a general matter, re-architecting processors in such a fashion is undesirable for a multitude of reasons, such as time and cost.
As the foregoing illustrates, what is needed in the art is a technique for more effectively handling increases in the minimum burst length associated with memory requests.